1. Field of the Invention
The present invention relates to a method for loading sub-processor of system in which a plurality of sub-processors serve as low-level processors with respect to the main processor. More particularly, the present invention relates to a loading procedure for loading plural sub-processors, concurrently, when utilizing broadcasting function.
2. Description of the Prior Art
Typically, in a system comprising a main processor and a plurality of sub-processors, the main processor and a plurality of sub-processors are interconnected via a repeater. FIG. 1 illustrates a conventional system in which main processor 1 and plural sub-processors 3 having N numbers are interconnected via a repeater 3. The repeater 3 is comprised of a numbers of N nodes connecting each to the corresponding sub-processors 3 having N numbers and a node connected to the main processor. The repeater 3 functions as a transmitter for sending data of a main processor to a link sub-processor.
That is, when a transmission path is demanded for intercommunicating the main processor with the link sub-processor, for instance, when data is transmitted between the main processor 1 and the sub-processor 3, or a loading procedure of a sub-processor is demanded with respect to a main processor, each node in the repeater is interconnected to provide a transmission path.
In the system when request of loading procedure with respect to the sub-processor occurs each sub-processor is loaded by control signal or a program running machine code in file, so main processor is interconnected to a sub-processor via the repeater 2. When plural sub-processors are loaded concurrently, the above mentioned procedure is repeated with respect to each sub-processor to enable all sub-processors to be loaded.
On the other hand, a broadcasting function means that the same data is transmitted concurrently to plural sub-processors from a main processor. At this time, the repeater 2 is interconnected between the main processor 1 and all the corresponding sub-processors 3. When broadcasting function is executed to all the N numbers sub-processors, for instance, a node of the main processor is common-connected to the a numbers of N nodes of the sub-processors as illustrated by a dotted line in FIG. 1, and thus the same data is transmitted to all the sub-processors comprising N numbers.
As in the system that plural sub-processors exist as a lower level processor with respect to the main processor, cable television network, various computer network and cable/radio communication network, etc. all exist. The radio communication network typically includes Code Division Multiple Access (CDMA) system, Time Division Multiple Access (TDMA) system, and Frequency Division Multiple Access (FDMA) system.
In CDMA system, Basestation Control Processor (BCP) is employed as a main processor, High capacity Inter Processor Communication Node Assembly (HINA) is employed as a repeater and Channel Card Controller (CCC) is employed as a sub-processor, which are schematically illustrated in FIG. 2.
BCP 11 stores Run Program, Operating System, and Utility Program for executing each CCC 13. When a channel card is loaded, the programs are transmitted to the corresponding CCC. Further, HINA 12 executes the function for interconnecting BCP 11 and CCC 13 in point-to-point or multipoint base, and CCC 13 downloads Run Program from BCP 11 and executes the function for running Utility Program.
In the above CDMA system, when CCC which is sub-processor is loaded, CCC 13 and BCP 11 are interconnected through HINA 12 in point-to-point base and thereafter the run program and the utility program are transmitted to CCC 13. At this time, when plural CCCs are loaded, the above procedure is repeated with respect to each CCC and all the channel cards to be loaded are loaded.
However, in such a system having plural sub-processors serving as a lower level with respect to the main processor, a conventional method for loading plural sub-processors has much request time to load the sub-processor due to that main processor which is interconnected to each sub-processor in point-to-point base and each sub-processor which is individually loaded in sequence. That is, when plural sub-processors are loaded, much time is required to repeatedly load sequentially repeatedly the same procedure with respect to each sub-processor.